AT32UC3C2512C-A2UT【PDF 40/110 页】IC MCU AVR32 512K FLASH 64TQFP

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32117DS–AVR-01/12

AT32UC3C

relative to EVBA. The autovector offset has 14 address bits, giving an offset of maximum 16384

bytes. The target address of the event handler is calculated as (EVBA | event_handler_offset),

not (EVBA + event_handler_offset), so EVBA and exception code segments must be set up

appropriately. The same mechanisms are used to service all different types of events, including

interrupt requests, yielding a uniform event handling scheme.

An interrupt controller does the priority handling of the interrupts and provides the autovector off-

set to the CPU.

4.5.1

System Stack Issues

Event handling in AVR32UC uses the system stack pointed to by the system stack pointer,

SP_SYS, for pushing and popping R8-R12, LR, status register, and return address. Since event

code may be timing-critical, SP_SYS should point to memory addresses in the IRAM section,

since the timing of accesses to this memory section is both fast and deterministic.

The user must also make sure that the system stack is large enough so that any event is able to

push the required registers to stack. If the system stack is full, and an event occurs, the system

will enter an UNDEFINED state.

4.5.2

Exceptions and Interrupt Requests

When an event other than scall or debug request is received by the core, the following actions

are performed atomically:

The pending event will not be accepted if it is masked. The I3M, I2M, I1M, I0M, EM, and

GM bits in the Status Register are used to mask different events. Not all events can be

masked. A few critical events (NMI, Unrecoverable Exception, TLB Multiple Hit, and

Bus Error) can not be masked. When an event is accepted, hardware automatically

sets the mask bits corresponding to all sources with equal or lower priority. This inhibits

acceptance of other events of the same or lower priority, except for the critical events

listed above. Software may choose to clear some or all of these bits after saving the

necessary state if other priority schemes are desired. It is the event source’s respons-

ability to ensure that their events are left pending until accepted by the CPU.

When a request is accepted, the Status Register and Program Counter of the current

context is stored to the system stack. If the event is an INT0, INT1, INT2, or INT3, reg-

isters R8-R12 and LR are also automatically stored to stack. Storing the Status

current event handling is completed. When exceptions occur, both the EM and GM bits

are set, and the application may manually enable nested exceptions if desired by clear-

ing the appropriate bit. Each exception handler has a dedicated handler address, and

this address uniquely identifies the exception source.

The Mode bits are set to reflect the priority of the accepted event, and the correct regis-

ter file bank is selected. The address of the event handler, as shown in Table 4-4 on

page 38, is loaded into the Program Counter.

The execution of the event handler routine then continues from the effective address calculated.

The rete instruction signals the end of the event. When encountered, the Return Status Register

and Return Address Register are popped from the system stack and restored to the Status Reg-

ister and Program Counter. If the rete instruction returns from INT0, INT1, INT2, or INT3,

registers R8-R12 and LR are also popped from the system stack. The restored Status Register

contains information allowing the core to resume operation in the previous execution mode. This

concludes the event handling.

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